SE-IR Corporation infrared camera products


CamIRa®

INFRARED FOCAL PLANE ARRAY EVALUATION and DEMONSTRATION SYSTEM
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Detailed Product Specification

Minimum System Requirements: top of page - next

Computer with 3 PCI (full height, full length) slots with 2 USB 2.0 ports, keyboard, VGA monitor,VGA display adapter, Windows XP. See example configurations below.

Recommended System Requirements:

Desktop or Server chassis with 2 PCI (full length, full height)slots and one 64 bit 66MHz PCI-X(full height, full length) slot, at least 2 available USB 2.0 ports, keyboard, track ball, high end 3d graphics card with dual monitor suuport, Windows XP Pro, 2Gbyte memory, dual processors, > 160 Gbyte hard disk and dual monitors, Windows 7, XP, Vista or Server  (32 or 64 bit).

 Example configurations

DESCRIPTION top of page - prev - next

The CamIRa® system is used to test and demonstrate state of the art IR focal plane arrays (FPAs). The standard system supports up to 4Meg pixel arrays, processing supports arbitrary size and organization (pixel order, multi color) FPA configurations. The system has a maximum pixel processing rate of 80 mega-pixels per second per tap. The system can be divided into three parts--the camera head, the digital electronics and the software.

CAMERA HEAD CamerHeadSideCoverOff and POWER SUPPLY PowerSupply top of page - prev - next

The camera head typically consists of an optional cryogenic LN2 dewar assembly for cooling the FPA (see SE-IR Corporation’s LN2 dewar products), clock driver electronics, low noise bias supplies, A/D cards for digitizing analog outputs, digital outputs can also be supported, an optional a 40 channel DVM for monitoring bias voltages and currents and for measuring FPA and a linear analog power supply

The camera head receives clocks through a parallel LVDS port from the PC based Pattern Generator.   Up to 30 clocks can be provided to the FPA though most FPAs require no more than 6. The clock drivers software programmable  rails and slew rates. The minimum rail to rail voltage is 0.25V and the maximum swing is 20.0V, in 5mV increments. The clock voltage range is -10.0V to +10.0V. The clock slew rate is adjustable from 1ns/V to 16ns/V.  There are 4 clocks channel per clock card (up to 4 clock cards in the standard camera head, up to 16 clock cards in the expanded head).

Four software programmable low noise bias supplies per bias card are available (up to 3 cards in the standard camera head, up to 6 cards in the expanded head) for providing FPA bias needs. They are used to provide power and any special voltages required by an FPA. They are software programmable from -10V to +10V in 20uV increments.

Up to 4 A/D cards can be use din the standard camera head, 8 cards in the expanded head, up to 16 cards in a custom configuration is also available. Software controlled offsets are added to the incoming signal to center the signal in the A/D range. The A/D gain is also software controlled. The A/D cards also support current output, voltage output and source/follower outputs requiring constant current supplies.  The 14 bit cards support signal ended and differential signals.  The 16 bit A/D card if single ended only.  There are 3 types of A/D cards available:

14 bit 10MSPS single channel: <100uVRMS (typ ~90uVRMS), software gain has 4 ranges for each board gain, there are 3 board gain ranges.  Gain ranges: from 0.8V  to 8V full scale.  Each channel also has constant current supplies are adjustable from 200 uA to 3.5 mA for each channel

14 bit 20MSPS  2 channel: <160uvRMS (typ ~120uVRMS), software gain has 4 ranges for each board gain, there are 16 board gain ranges.  Gains ranges: from 0.3V to 4.5V full scale

16 bit 1.25MSPS 4 channel: <50uVRMS (typ ~30uVRMS), software gain has 4 ranges for each board gain, there are 3 board gain ranges.  Gain ranges: from 0.66V  to 8V full scale. Each channel also has constant current supplies are adjustable from 200 uA to 3.5 mA for each channel

The aggregate sampling rate for all channels is limited to 80 mega-samples per second in the standard system. Multiple  tap configuration can be available. There are four special convert clocks available to control when sample conversion occurs. Each of these clocks can be delayed up to 1 msec in 2 nsec steps. This allows conversion of the output to occur at the optimum sampling point avoiding clock correlated noise spikes that may be present in the output channel while allowing for optimum settling. The A/D output are then multiplexed into a single 16-bit wide video data stream. This data along with sync signals are sent over a high speed LVDS parallel interface to the digital electronics.

The standard interface cables to the clocks and digital video signals are 25 feet long and use SCSI-3 differential cables (the interface is NOT SCSI-3). Cables up to 100 feet can be used at full rate. Longer cables can be used at slower clock rates. This allows the camera head and digital electronics to be separated as may be required in some applications.

DIGITAL ELECTRONICS  top of page - prev - next

The digital electronics consist of three parts--a Pattern Generator board (PCI for power, USB for control), a pipeline DSP  board (PCI for power, USB for control), and a frame grabber board (PCI-X for max. throughout). All the board have a universal PCI bus interface so they can be use in any PCI or PCI-X slot.  They can not be plugged into a PCI-express slot.

The pattern generator board is a programmable timing generator with special features for operating FPAs. Patterns are defined as subpatterns. These subpatterns are output according to a control program. Up to 4 levels of looping are available along with synchronizing to external signals. The special features include the A/D conversion clocks mentioned earlier and the integration control clocks for controlling the integration time for a frame. There are up to four independent integration clocks that can be generated. Each integration clock can be duty cycle controlled and changed without stopping or reloading the timing patterns. The integration clocks can also be multiplexed together to allow super frames to be constructed consisting of two or four sequential frames with each frame having a different integration time. Sync signals are sent to the camera head and then returned to the digital signal processing electronics. This gives the sync signals the same delays as the FPA clock and data signals so that they are independent of cable length.

The pattern generator has 3 clock crystal and one pll frequency generator.  The crystals allows for very low jitter clock when short integrations time are used (<30usec).  The clock synthesizer allows the user to select clock rates from 20 KHz to 75 MHz with 5-1/2 digits of resolution.

The video output of of the camera head is the input to the FB40 frame grabber board. The frame grabber board captures 16 wide data at up to 80MSPS.  Maximum frame rate is 500 KHz.  It is a PCI-X 64 bit bit card (does not require Windows 7, 8, XP, Vista or Server 64 bit).  It uses scatter gather DMA to stream data into the PC’s memory.  Native Windows driver are compatible with Windows 7, 8, XP, Vista or Server either 32 bit or 64 bit.  There DLLs for the frame grabber that allow for custom acquisition software.  There also DirectShow, Video for Windows and MATLAB Acquisition filters available in the software for data capture and processing.  The frame grabber is also support in IO Industries Streams software

SOFTWARE        

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The CamIRa ® software is very extensive and includes all the controls needs to operate and control FPAs through the hardware. The software is used to setup, control and perform analysis on image data coming from the FPA. This includes 2-point correction, image subtraction, image statistics, FPA parameters setup (including frame rate and intergration time), image setup and orientation, image capture functions, display control and many other functions.  It also allows Winsock control over network or local machine.  This allows user to control the software, hardware and FPA along with data capture through programs such as Python, IDL, LabView, Matlab and customer written software.  The software operates under Windows 7,  XP, Vista or Server. Sample code and libraries are compatible with Microsoft Visual Studio 2005 or later.  The software also includes image processing filters for creating DirectShow processing chains.  This is used for real-time display of imaging using the CamIRa® software.  The filter chain editor in the software allows construction of complex image processing chains that the user can use to evaluate image processing techniques on live and stored data.  A TCIP socket interface allows for remote control of camera settings along with remote data capture.  This allows the user to operate the software from anywhere on a network.

Optional software for radiometric measurement and reporting is QuickIRtest by Dave Vincent.  Please contact SE-IR Corporation for more details.


Powerpoint VUgraph presentation of architecture 


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Warranty 1 year parts and labor does not include normal wear and tear, abuse or modifications made by customer.
Software is provided under a License Agreement.
Terms are net 30 days on approved credit. All orders are F.O.B. Goleta, CA unless quoted otherwise.
SE-IR Corporation reserves the right to change prices or configuration at any time without notice.


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SE-IR Corporation


87A Santa Felicia Drive
Goleta, CA 93117 USA
(805) 571-6800 Voice
(805) 571-3434 FAX
e-mail: gregpierce at seir.com